This invention relates to interconnection networks and, more particularly, networks providing optimized communication pathways in multinodal systems. The invention has application, by way of example, in bus structures of multiprocessor digital data processing systems.
The art discloses a number of structures for connecting elements within multinodal systems. A wide variety of such arrangements are used in the digital data processing field, where designers have gone to great lengths to devise mechanism for coupling system functional units, e.g., central processors, memories and input/output controllers, to achieve maximum throughput and other desired characteristics.
One prior art approach, the so-called multiport system, utilizes separate buses to connect individual shared memory units and multiple processing units. In a multiport system having four processors and four memory units, for example, every processor has its own dedicated bus. Each of these buses is connected to the individual memory units. Interface modules having four ports are provided on the memory units to oversee communications between them and the processors and, particularly, to control which processor has access to the associated memory at any given moment.
In prior art crossbar systems, a switching array is interposed between functional units to establish temporary communication paths. Nodes within the system, e.g., the central processing units, peripheral control units, and memory modules, have their own dedicated buses which are interconnected in the form of a grid with switches at each intersection. These switches respond to command and address signal received from the nodes to open communication paths formed on a transaction-by-transaction basis. Once a transaction is completed, its pathway is closed, leaving that portion of the grid accessible by the other units.
The "common bus" system employs a single system bus to handle communications between multiple nodes. A multiprocessor system having a plurality of central processors sharing a single memory module, for example, permits only one processor at a time to transfer information with the memory module. Other processors requiring access to the memory unit wait their turn and arbitrate for the bus before proceeding. The related dual-bus system utilizes a main system bus to connect a set of local common bus-type systems. A controller unit interfaces each local network to the main bus, transferring signals between them as required.
These prior art approaches have a number of drawbacks. The multiport and crossbar networks, although offering a high transmission bandwidth, become unduly complex and costly as the number of nodes increase. The common-bus and dual-bus systems, while less hardware intensive, form bottlenecks at their shared resources, e.g., the main system bus and memory and, therefore, have relatively narrow transmission bandwidths.
In view of the foregoing, an object of this invention is to provide an improved system for connecting processing elements of a multinodal system. Another object of the invention is to provide an improved structure for linking multiple nodes of computing and signal processing systems. A further object is to provide a multinodal computing and signal processing system which maximizes communication bandwidth and minimizes hardware cost and complexity. Still another object is to provide an improved bus structure for a digital data processing system.